Repeat Exercise for the Xilinx XC4000 FPGA macrocell (CLB) shown in Figure 9-45.ExerciseSt...

Repeat Exercise for the Xilinx XC4000 FPGA macrocell (CLB) shown in Figure 9-45.

Exercise

Study the structure of the Xilinx XC9500 CPLD macrocell in Figure 9-41, and determine the largest number of inputs that can be accommodated in an XOR (parity) function that fits in a single macrocell, assuming that “steered” product terms from other macrocells are not used (they are slower). Describe which macrocell resources are used to achieve this result and how they are used. Hint: Using most HDL tools, you can write and synthesize HDL programs for 2-, 3-, 4-, and 5-input XOR functions and look at the resulting, fitted equations.