Create a VHDL type, based on IEEE 1164, that models open-collector outputs, where tying ou...

Create a VHDL type, based on IEEE 1164, that models open-collector outputs, where tying outputs together creates a wired-AND function. You should also model a pull-up resistor element such that if there is no pull-up resistor and no device is driving the bus, then an “unknown” signal is produced. Test your definitions by modeling the circuit in Figure for all input combinations, both with and without R1 present.

Figure