Write a structural VHDL or Verilog program for the multibit parity function that you desig...

Write a structural VHDL or Verilog program for the multibit parity function that you designed in Exercise 1 and target it to an XC9500 CPLD. Does the final, fitted circuit have just two levels of delay? If not, why not, and can you discover any tricks or tools that force the synthesis tool to do “the right thing”?

Exercise 1

Based on your answer for Exercise 2, determine the number of inputs in the largest XOR (parity) function that can be designed in just two levels of XC9500 macrocells, again assuming that “steered” product terms from other macrocells are not used. Draw a block diagram showing how the function is partitioned into macrocells; how many are used?

Exercise 2

Study the structure of the Xilinx XC9500 CPLD macrocell in Figure 9-41, and determine the largest number of inputs that can be accommodated in an XOR (parity) function that fits in a single macrocell, assuming that “steered” product terms from other macrocells are not used (they are slower). Describe which macrocell resources are used to achieve this result and how they are used. Hint: Using most HDL tools, you can write and synthesize HDL programs for 2-, 3-, 4-, and 5-input XOR functions and look at the resulting, fitted equations.