Repeat Exercise with 8-bit buses using VHDL or Verilog, and targeting a CPLD or FPGA. Determine how many internal resources are used by the design.
Exercise
Design a customized multiplexer with five 4-bit input buses A, B, C, D, and E, selecting one of the buses to drive a 4-bit output bus T according to Table. You may use no more than three MSI and SSI ICs.
Table
S2 | S1 | S0 | Input to Select |
0 | 0 | 0 | A |
0 | 0 | 1 | B |
0 | 1 | 0 | A |
0 | 1 | 1 | C |
1 | 0 | 0 | A |
1 | 0 | 1 | D |
1 | 1 | 0 | A |
1 | 1 | 1 | E |
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