Repeat the Exercise, adding two control inputs C1 and CO such that the output bus Y is all 0s, all 1s, the selected input bus, or its complement, depending on whether C1 Co is 00, 01, 10, or 11 respectively.
Exercise
Write a VHDL or Verilog program for a customized multiplexer with four 8-bit input buses P, Q, R, T, and three select inputs S2–S0 that choose one of the buses to drive an 8-bit output bus Y according to Table.
Table
S2 | S1 | S0 | Input to Select |
0 | 0 | 0 | P |
0 | 0 | 1 | P |
0 | 1 | 0 | P |
0 | 1 | 1 | Q |
1 | 0 | 0 | P |
1 | 0 | 1 | P |
1 | 1 | 0 | R |
1 | 1 | 1 | T |
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