Write a version of the Verilog 74xl48-like priority-encoder module of Table 6-31 in which the for loop starts with the highest-priority input and searches down, using the Verilog disable statement to exit the loop when an asserted input is found. Synthesize both Table 6-31 and your module to a CPLD and compare the synthesized results. (Note: disable is not supported by all Verilog tools.)
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