Write a structural VHDL or Verilog program that instantiates a single 2-input OR gate and...

Write a structural VHDL or Verilog program that instantiates a single 2-input OR gate and the BUT gate component of Exercise 1 to realize the logic function in Exercise 2. Write a test bench that checks your circuit’s output for all 16 possible input combinations and displays a message if there’s an error.

Exercise 1

Write a behavioral-style VHDL or Verilog program for the BUT gate defined in Exercise 3.

Exercise 2

Butify the function F = ∑w, x, y, z(5, 7, 10, 11, 13, 14). That is, show how to perform F with a single BUT gate as defined in Exercise 3 and a single 2-input OR gate.

Exercise 3

Some people think that there are four basic logic functions. AND, OR, NOT, and BUT. Figure is a possible symbol for a 4-input, 2-output BUT gate. Invent a useful, nontrivial function for the BUT gate to perform. The function should have something to do with the name (BUT). Keep in mind that, due to the symmetry of the symbol, the function should be symmetric with respect to the A and B inputs of each section and with respect to sections 1 and 2. Describe your BUT’s function and write its truth table.

Figure