Starting with the Verilog module in Table 6-26, write a Verilog module for a seven-segment decoder with the following enhancements:
• The outputs are all active low.
• Two new inputs, ENHEX and ERRDET, control segment-output decoding.
• If ENHEX = 0, the outputs match the behavior of a 74x49.
• If ENHEX = 1, then the outputs for digits 6 and 9 have tails, and the outputs for digits A-F are controlled by ERRDET.
• If ENHEX = 1 and ERRDET = 0, then the outputs for digits A-F look like the letters A-F, as in the original program.
• If ENHEX = 1 and ERRDET = 1, then digits A-F look like the letter S.
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