Find a gate-level design for the BUT gate defined in Exercise 1 that uses a minimum number...

Find a gate-level design for the BUT gate defined in Exercise 1 that uses a minimum number of transistors when realized in CMOS. You may use inverting gates with up to 4 inputs, AOI or OAI gates, transmission gates, or other transistor- level tricks. Write the output expressions (which need not be two-level sums of products), and draw the logic diagram.

Exercise 1

A possible definition of a BUT gate (Exercise 2) is “Y1 is 1 if A1 and B1 are 1 but either A2 or B2 is 0; Y2 is defined symmetrically.” Write the truth table and find minimal sum-of-products expressions for the BUT-gate outputs. Draw the logic diagram for a NAND-NAND circuit for the expressions, assuming that only uncomplemented inputs are available. You may use gates from 74x00, ’04, ’10, ’20, and ’30 packages.

Exercise 2

Some people think that there are four basic logic functions. AND, OR, NOT, and BUT. Figure is a possible symbol for a 4-input, 2-output BUT gate. Invent a useful, nontrivial function for the BUT gate to perform. The function should have something to do with the name (BUT). Keep in mind that, due to the symmetry of the symbol, the function should be symmetric with respect to the A and B inputs of each section and with respect to sections 1 and 2. Describe your BUT’s function and write its truth table.

Figure