Design a 3-bit equality checker with six inputs, SLOT[2–0] and GRANT[2–0], and one active-low output, MATCH _L. The SLOT inputs are connected to fixed values when the circuit is installed in the system, but the GRANT values are changed on a cycle-by-cycle basis during normal operation of the system. Using only SSI and MSI parts that appear in Tables 6-2 and 6-3, design a comparator with the shortest possible maximum propagation delay from GRANT[2–0] to MATCH_L. (Note:The author had to solve this problem “in real life” to shave 2 ns off the critical-path delay in a 25-MHz system design.)
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