For the CMOS op-amp in Figure 13.14, the dc biasing is designed such that Iset = Iq — Idq8...

For the CMOS op-amp in Figure 13.14, the dc biasing is designed such that Iset = Iq — Idq8 = 200 µA. The transistor parameters are VTN = 0.5 V, , and λp = 0.025 V–1. The transistor width-to-length ratios are (W/L)1,2 = 50, (W/L)3,4 = 15,(W/L)5,6,8 = 10, and (W/L)7 = 30. Determine the small- signal voltage gains of the input and second stages, and the overall voltage gain.