Consider the BiFET differential input stage in Figure P13.61, biased with power supply voltages V+ and V‑. Let = V+ = Vs. (a) Design the bias circuit such that IREF2 = 100µA for supply voltages in the range 3 ≤ Vs≤ 12 V. Determine VZk, R3, and the JFET parameters, (b) Determine the value of R4 such that IO1 = 500µA when V+ = 12 V.
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