Consider the CMOS op-amp in Figure 13.14. Design a complementary CMOS circuit in which each element is replaced by its complement. The bias voltages are ±5 V. The threshold voltage is | V for all transistors, and λ = 0.01 V-1 for all transistors. Design reasonable width-to- length ratios and bias currents to provide a minimum overall voltage gain of at least 20,000.
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