The CMOS op-amp in Figure 13.14 is biased at V+ = 5 V and V– = –5 V. Let RSet = 50kΩ. Assu...

The CMOS op-amp in Figure 13.14 is biased at V+ = 5 V and V– = –5 V. Let RSet = 50kΩ. Assume transistor parameters of VTn = 0.7 V,  and λp = 0.04 V-1. The transistor width-to-length ratios are (W/L)3,4 = 15, (W/L)7 = 30, and (W/L) = 50 for all other transistors, (a) Determine Iset, IQ, and IDQ7 (b) Find the small-signal voltage gains of the input and second stages, and the overall voltage gain.