(a) Design a three-input NMOS NOR logic gate with depletion load such that VoL(max) = 50 mV and such that the maximum power dissipation is 50μW. Let VDD = 2.5 V. The transistor parameters are k'n = 100μA/V2, VTND = 0.4 V, and VTNL = -0.6 V. (b) Using the results of part (a), determine VOL when all inputs are a logic 1.
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