The transistor parameters for the circuit in Figure P16.21 are: VTN = 0.8 V for all enhanc...

The transistor parameters for the circuit in Figure P16.21 are: VTN = 0.8 V for all enhancement-mode devices, VTN= -2 V for the depletion-mode

devices, and k'n = 60 μA/V2 for all devices. The width-to-length ratios of ML2 and ML1are 1, and those for MD2, MD3, and MD4 are 8. (a) For vx = 5 V, output v01 is 0.15 V, and the power dissipation in this inverter is to be no more than 250 μW. Determine (W/L)ML1 and ( W/L)MDI. (b) For vx = vy =0, determine v02.