Consider the NMOS R-S flip-flop in Figure 16.63 biased at VDD= 2.5 V. The threshold voltages are 0.4V (enhancement-mode devices) and -0.6 V (depletion-mode devices). The conduction parameters are K3 = K6=40μA/V2, K2= Ks= IOOJLA/V2, and KI= K4= 150JLA/V2. If Q= logic0 and Q= logic 1 initially, determine the voltage at S that will cause the flip-flop to change states.
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