A 256-K memory is organized in a square array and uses the NMOS NOR decoder in Figure 16.73(b) for the row- and column-decoders, (a) How many inputs does each decoder require? (b) What input to the row decoder is required to address row (i) 52, (ii) 129, and (iii) 241? (c) What input to the column decoder is required to address column (i) 24, (ii) 165, and (iii) 203?
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