A one-transistor DRAM cell is composed of a 0.05 pF storage capacitor and an NMOS transistor with a 0.5 V threshold voltage. A logic 1 is written into the cell when both the data line and row-select line are raised to 3 V. Sensing circuitry permits the stored charge to decay to 50 percent of its original value. Refresh occurs every 1.5 ms. Determine the maximum allowed leakage current that can exist.
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