An NMOS inverter with saturated load is shown in Figure 16.5(a). The bias is VDD = 3 V and the transistor threshold voltages are 0.5 V. (a) Find the ratio KD/KL such that v0 = 0.25 V when v1 = 3 V. (b) Repeat part (a) for v1=2.5 V. (c) If W/L=1 for the load transistor, determine the power dissipation in the inverter for parts (a) and (b).
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