(a) Determine the noise margins of a CMOS inverter biased at VDD = 3.3 V with (W/L)n = 2 and (W/L)p = 5. Assume VTN = 0.4 V and VTP =-0.4 V. (b) Repeat part (a) for (W/L)n = 4 and (W/L)p = 12.
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