Consider a general sense amplifier configuration shown in Figure 16.82 for a dynamic RAM. Assume that each bit line has a capacitance of 1 pF and is precharged to 4 V. The storage capacitance is 0.05 pF, the reference capacitance is 0.025 pF, and each is charged to 5 V for a logic 1 and to 0 V for a logic 0. The Ms and MR gate voltages are 5 V when each cell is addressed and the transistor threshold voltages are 0.5 V. Determine the bit line voltages v1 and v2 after the cells are addressed for the case when (a) a logic 1 is stored and (b) a logic 0 is stored.
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