Consider the CMOS RAM cell and data lines in Figure 16.76 biased at VDD = 2.5 V. Assume tr...

Consider the CMOS RAM cell and data lines in Figure 16.76 biased at VDD = 2.5 V. Assume transistor parameters K'n=80μA/V2, K'p=35μA/V2,VTN=0.4V, VTP=-0.4V,W/L=2 (MN1 and MN2), W/L=4(MP1 and MP2), and W/L=1(all other transistors). If Q=0 and determine the steady-state values of D and after the row has been selected. Neglect the body.