(a) Redesign the resistive load inverter in Figure 16.3(a) so that the maximum power dissipation is 0.25 mW with VDD = 3.3 V and v0 = 0.15 V when the input is a logic 1. (b) Using the results of part (a), what is the input voltage range when the transistor is biased in the saturation region?
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