(a) Design the saturated load inverter circuit in Figure 16.5(a) such that the power dissipation is 0.30 mW and the output voltage is 0.08 V for v1 = 1.4 V. The circuit is biased at VDD = 1.8 V and the transistor threshold voltage of each transistor is VTNO = 0.4 V. (b) Using the results of part (a), find the range of input voltage such that the driver transistor is biased in the saturation region.
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