Consider the NMOS inverter with depletion load in Figure 16.7(a). Let VDD = 1.8 V, and assume VTND = 0.3 V and VTNL = -0.6 V. (a) Design the circuit such that the power dissipation is 80 μW and the output voltage is v0= 0.06 V when v1 is a logic 1. (b) Using the results of part (a), determine the transition points for the driver and load transistors, (c) If (W/L)D found in part (a) is doubled, what is the maximum power dissipation in the inverter and what is v0 when V1 is a logic 1?
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