Consider a four-input CMOS NOR logic gate. Determine the W/L ratios of the transistors to provide for symmetrical switching based on the CMOS inverter design with (W/L)n = 2 and (W/L)P = 4. (b) If the load capacitance of the NOR gate doubles, determine the required W/L ratios to provide the same switching speed as the logic gate in part (a).
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