The enhancement-load transistor in the NMOS inverter in Figure P16.8 has a separate bias a...

The enhancement-load transistor in the NMOS inverter in Figure P16.8 has a separate bias applied to the gate. Assume transistor parameters of Kn=1mA/V2for  MD, Kn=0.4mA/V2 for ML, and VTN=1V for both transistors. Using the appropriate logic 0 and logic 1 input voltages, determine V0H and V0L for: (a) VB = 4 V, (b) VB = 5 V, (c) VB = 6 V, and (d) VB = 7 V.