The NMOS inverter with depletion load is shown in Figure 16.7(a). The bias is VDD = 2.5 V. The transistor parameters are VTND=0.5 V and VTNL= -1V. The width-to-length ratio of the load device is W/L = 1. (a) Design the driver transistor such that v0 = 0.05 V when the input is a logic 1. (b) What is the power dissipated in the circuit when v1 = 2.5 V?
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